2026-03-12
Mst. Rokeya Khatun, Fahmid Al Farid, Sharith Dhar, Md. Saiful Islam, Jia Uddin, Hezerul bin Abdul Karim
Automated interpretation of wafer maps is central to manufacturing quality monitoring. Identifying rare defects with less detailed wafer maps is a challenging task. Moreover, class imbalance, heavyweight backbones, and limited model transparency are constraints for the real-world deployment of defective wafer identification. However, a nine-class wafer-map classifier is required that maintains high accuracy under tight parameter and compute budgets and provides decision-level interpretability, despite long-tailed class distributions. To address this issue, a compact convolutional network is presented for wafer-map classification on standardized low-resolution inputs. The architecture uses two convolution–pooling stages, followed by a modified convolutional block attention module (CBAM). Channel attention is realized via a shared multilayer perceptron with batch normalization for stable reweighting, while spatial attention uses a multi-scale gate to emphasize ring-like, edge-localized, and streak patterns. A compact dense head with softmax produces nine class probabilities, with a total footprint of approximately 0.15M parameters. Class imbalance is mitigated through a training-only convolutional autoencoder that generates minority samples via latent feature variation, together with a controlled reduction in the dominant None class. Validation and test sets remain unchanged. A fixed-seed protocol ensures reproducibility, and performance is evaluated using accuracy and macro-averaged precision, recall, and F1. On a balanced benchmark derived from the WM-811K dataset, the model achieves 99.88% test accuracy with near-ceiling macro-F1 while using a small fraction of the parameters required by transfer learning and transformer baselines and consistently outperforming conventional convolutional neural network (CNN) backbones. Post-training interpretability analyses with Grad-CAM, integrated gradients (IG), and occlusion show alignment between salient regions and physically meaningful defect morphology. Ablation studies indicate complementary gains from latent feature augmentation and attention mechanisms, while robustness checks with input noise and reduced training support show graceful degradation. The resulting pipeline is accurate, lightweight, and transparent, making it suitable for inline screening scenarios.
DOI: 10.3389/felec.2026.17507072026-02-24
Sachin Maheshwari, Mike Smart, Himadri Singh Raghav, Themis Prodromakis, Alexander Serb
This paper presents a highly energy-efficient adiabatic capacitive neuron (ACN) hardware implementation of an artificial neuron (AN), with improved energy efficiency, robustness, and scalability over previous work. A single-neuron ACN with 12 one-bit capacitive synapses is implemented in 0.18 μm CMOS technology, supporting both positive and negative synaptic weights. A novel threshold logic (TL) circuit is introduced to realize the binary AN activation function, explicitly designed to minimize input-referred offset and ensure robust decision making under dynamic adiabatic operation. The TL performance is evaluated across three process corners and five temperatures ranging from –55 °C to 125 °C. Post-layout simulations show that the proposed TL achieves a maximum rising and falling offset voltage of 9 mV, compared to 27 mV (rising) and 5 mV (falling) for a conventional TL implementation across process and temperature variations. The proposed ACN achieves over 90% total synapse energy savings (over 12× improvement) relative to an equivalent non-adiabatic CMOS capacitive neuron (CCN) over operating frequencies from 500 kHz to 100 MHz. A 1000-sample Monte Carlo analysis incorporating process variation and mismatch confirms consistent energy savings exceeding 90% in the synapse energy profile. Supply voltage scaling further demonstrates sustained energy savings above 90%, except for the all-zero input condition, without loss of functionality. These results demonstrate that adiabatic charge recovery, combined with a robust low-offset threshold logic design, enables substantial energy reduction while maintaining reliable neuron operation across wide operating conditions.
DOI: 10.3389/felec.2026.17432652025-10-23
Xintai Wang, Maksim Kuznetcov, Wenfeng Jiang, Zhongyu Tang, Zhangchenyu Wei, Aili Zhang, Naixu Wei, Xiaoying Li
This review investigates the revolutionary potential of printed RFID technology in enabling next-generation IoT systems through sustainable manufacturing. The analysis systematically evaluates emerging conductive ink formulations, including metallic nanoparticles, carbon-based nanomaterials, MXenes, and hybrid composites, while assessing their performance trade-offs in electrical conductivity, environmental stability, and printing compatibility. Fundamental design strategies for high-performance antennas are examined, focusing on impedance matching optimization, radiation pattern control, and substrate-material synergy. Advances in printing methodologies such as inkjet deposition, screen printing, and direct ink writing are comparatively analyzed, with particular attention to the trade-off between performance and efficiency in high-resolution patterning versus industrial-scale production. Technical bottlenecks restricting commercial application are critically evaluated, emphasizing material property limitations and performance variations induced by the printing process. Finally, the study proposes three synergistic innovation pathways: intelligent material discovery through machine learning algorithms, multi-parameter simulation-guided antenna design, and hybrid manufacturing integrating multiple printing technologies. These integrated approaches aim to accelerate the transition from prototype development to industrial deployment of printed RFID systems. This comprehensive assessment provides actionable insights for advancing eco-friendly, mass-producible RFID solutions that meet the escalating demands of ubiquitous IoT connectivity across various smart environments.
DOI: 10.3389/felec.2025.16974492025-09-24
Tingyun Gu, Yu Wang, Yiheng Liu, Qihui Feng, Qiao Peng
Battery energy storage systems (BESSs) are required to provide frequency support to the grid in some cases, which increases the charge-discharge cycles of battery and accelerates its aging, especially in primary frequency control (PFC). However, the conventional PFC of BESS mainly focuses on the frequency support performance without adequately considering battery health. This paper proposes an adaptive PFC of BESS for battery aging mitigation, which adopts a novel overshoot-tolerant principle to recover the state of energy (SOE) of battery. Once the frequency support demand aligns with the SOE recovery demand, the BESS responds to the frequency deviation in a reverse way. Then, the battery can be charged or discharged more vigorously, and the SOE of battery can be adequately maintained at an ideal level. A multi-objective online optimization model is proposed to update the optimal PFC coefficient, which is solved by the non-dominated sorting genetic algorithm (NSGA-II). The simulation results verify the proposed method, which can effectively recover the SOE of battery with an improved frequency support performance. Moreover, the case study results also validate that the aging of battery can be mitigated by recovering the SOE.
DOI: 10.3389/felec.2025.16339512025-09-15
Utkarsha Bhetuwal, Jiang Zhou, Xuejun Fan
This paper presents a closed-form analytical model for predicting shear strain in chip-on-board assemblies with an array of solder balls. While the classical analytical formula estimates shear strain based on a configuration with a single solder joint at each end of the chip, it fails to account for the distributed nature of real assemblies. By applying compatibility conditions along the chip/solder ball and PCB/solder ball interfaces, and employing beam theory, the proposed model incorporates key geometric and material parameters, including chip and PCB dimensions, solder ball diameter, height, pitch, and elastic moduli, enabling accurate prediction of mechanical response under thermal loading. Results show that the classical model overestimates shear strain by more than 50 times compared to finite element analysis (FEA), whereas the proposed method yields results consistent with FEA. Hence, the proposed analytical solution presented in the paper demonstrates a significant improvement over the classical formula in prediction of shear strain. The new model reveals that in a fully populated array layout, the maximum shear strain at the outermost solder joint remains nearly constant with increasing chip size. The analysis also indicates that inner solder joints contribute minimally to mechanical support, suggesting that depopulated array designs may not compromise reliability. Additional parametric studies demonstrate that reducing the thickness or stiffness of the chip or PCB decreases overall strain levels. These findings are validated by finite element simulations. The paper concludes with a discussion of future work to address normal strain effects and inelastic behaviors in solder joints.
DOI: 10.3389/felec.2025.16487212025-08-21
Tianren Zhao, Yanhui Zhang, Minghao Wang, Wei Feng, Shengxian Cao, Gong Wang
With the widespread application of lithium-ion batteries in electric vehicles and energy storage systems, health monitoring and remaining useful life prediction have become critical components of battery management systems. To address the challenges posed by the high nonlinearity and long-term dependency in battery degradation modeling, this paper proposes a deep hybrid architecture that integrates Long Short-Term Memory networks with Transformer mechanisms, aiming to improve the accuracy and robustness of RUL prediction. Firstly, time-series samples are constructed from raw battery data, and physically consistent temperature-derived features—including average temperature, temperature range, and temperature fluctuation—are engineered. Data preprocessing is performed using standardization and Yeo-Johnson transformation. The model employs LSTM modules to capture local temporal patterns, while the Transformer modules extract global dependencies through multi-head self-attention mechanisms. These complementary features are fused to enable joint modeling of battery health states. The regression task is optimized using the Mean Squared Error loss function and trained with the Adam optimizer. Experimental results on the MIT battery dataset demonstrate the proposed model achieves excellent performance in a 7-step multi-point prediction task, with a Root Mean Square Error of 0.0085, Mean Absolute Percentage Error of 0.0200, and a coefficient of determination of 0.9902. Compared with alternative models such as MC-LSTM and XGBoost-LSTM, the proposed model exhibits superior accuracy and stability. Residual analysis and visualization further confirm the model’s unbiased and stable predictive capability. This study shows that the LSTM-Transformer hybrid architecture offers significant potential in modeling complex battery degradation processes and enhancing RUL prediction accuracy, providing effective technical support for the development of intelligent battery health management systems.
DOI: 10.3389/felec.2025.16543442025-07-03
Li Zhang, Olga Krestinskaya, Mohammed E. Fouda, Ahmed M. Eltawil, Khaled Nabil Salama
With the rapid development of machine learning, Deep Neural Network (DNN) exhibits superior performance in solving complex problems like computer vision and natural language processing compared with classic machine learning techniques. On the other hand, the rise of the Internet of Things (IoT) and edge computing set a demand on executing those complex tasks on corresponding devices. As the name suggested, deep neural networks are sophisticated models with complex structures and millions of parameters, which overwhelm the capacity of IoT and edge devices. To facilitate the deployment, quantization, as one of the most promising methods, is proposed to alleviate the challenge in terms of memory usage and computation complexity by quantizing both the parameters and data flow in the DNN model into formats with shorter bit-width. Consistently, dedicated hardware accelerators are developed to further boost the execution efficiency of DNN models. In this work, we focus on Convolutional Neural Network (CNN) as an example of DNNs and conduct a comprehensive survey on various quantization and quantized training methods. We also discuss various hardware accelerator designs for quantized CNN (QCNN). Based on the review of both algorithm and hardware design, we provide general software-hardware co-design considerations. Based on the analysis, we discuss open challenges and future research directions for both algorithms and corresponding hardware designs of quantized neural networks (QNNs).
DOI: 10.3389/felec.2025.1469802